(1) Field of the Invention
The present invention relates to a semiconductor memory device, more particularly to a semiconductor memory device such as a dynamic random access memory or other device wherein, when an operation is performed by the nibble mode or page mode, the period of the output data can be increased.
(2) Description of the Related Art
In a dynamic random access memory, operation under a nibble mode (4-bit block of a word), page mode, etc. enables a plurality of bits of data to be read out at a high speed. However, when reading out data under the nibble mode, page mode, etc., the time interval of each bit of the read out signal becomes extremely short and the period of the output data becomes considerably short. When the period of the output data is too short, the circuits connected to the memory device cannot respond sufficiently and accurate data readout becomes impossible. Therefore, even in data readout under the nibble mode, page mode, etc., it is desirable that the period of each bit of the output data be made as long as possible.
In a conventional memory device, each successive data readout in the nibble mode or page mode is output after the fall of an inverted column address strobe signal and is reset at the rise of the inverted column address strobe signal. Therefore, the time period of each output data is considerably short.
To eliminate this disadvantage, there is known another memory device, for example, the Model 2716 16K RAM from Intel Co., USA. In this memory device, each output data is reset at the fall of the inverted column strobe signal, thereby considerably expanding the time period of the output data. However, this memory device has the disadvantage of competition occurring between outputs of a plurality of memory chips when a plurality of memory chips are combined to form a large capacity memory system as explained in detail later.